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Source-Synchronous Networks-On-Chip [electronic resource] : Circuit and Architectural Interconnect Modeling / by Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra.

By: Mandal, Ayan [author.].
Contributor(s): Khatri, Sunil P [author.] | Mahapatra, Rabi [author.] | SpringerLink (Online service).
Material type: materialTypeLabelBookPublisher: New York, NY : Springer New York : Imprint: Springer, 2014Description: XIII, 143 p. 95 illus., 10 illus. in color. online resource.Content type: text Media type: computer Carrier type: online resourceISBN: 9781461494058.Subject(s): Engineering | Computer science | Electronics | Systems engineering | Engineering | Circuits and Systems | Processor Architectures | Electronics and Microelectronics, InstrumentationDDC classification: 621.3815 Online resources: Click here to access online
Contents:
Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work.
In: Springer eBooksSummary: This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.
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Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work.

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks.  The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized.  Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.   • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.

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