000			01829nam a22004935i 4500
001			978-3-540-32080-7
003			DE-He213
005			20130515021358.0
007			cr nn 008mamaa
008			100929s2005 gw | s |||| 0|eng d
020			_a9783540320807 _9978-3-540-32080-7
024	7		_a10.1007/11556930 _2doi
050		4	_aQA76.9.L63
072		7	_aUYF _2bicssc
072		7	_aCOM036000 _2bisacsh
082	0	4	_a621.395 _223
100	1		_aPaliouras, Vassilis.
245	1	0	_aIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation _h[electronic resource] : _b15th International Workshop, PATMOS 2005, Leuven, Belgium, September 21-23, 2005. Proceedings / _cedited by Vassilis Paliouras, Johan Vounckx, Diederik Verkest.
260			_aBerlin, Heidelberg : _bSpringer Berlin Heidelberg, _c2005.
300			_bdigital.
490	0		_aLecture Notes in Computer Science, _x0302-9743 ; _v3728
650		0	_aComputer science.
650		0	_aLogic design.
650		0	_aOperating systems (Computers).
650		0	_aComputer aided design.
650		0	_aComputer engineering.
650	1	4	_aComputer Science.
650	2	4	_aLogic Design.
650	2	4	_aPerformance and Reliability.
650	2	4	_aProcessor Architectures.
650	2	4	_aArithmetic and Logic Structures.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
650	2	4	_aElectrical Engineering.
700	1		_aVounckx, Johan.
700	1		_aVerkest, Diederik.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9783540290131
830		0	_aLecture Notes in Computer Science, _x0302-9743 ; _v3728
856	4	0	_uhttp://dx.doi.org/10.1007/11556930
912			_aZDB-2-SCS
912			_aZDB-2-LNC
999			_c76707 _d76707