000 01493nam a22004335i 4500
001 978-0-387-48550-8
003 DE-He213
005 20130515020511.0
007 cr nn 008mamaa
008 100301s2007 xxu| s |||| 0|eng d
020 _a9780387485508
_9978-0-387-48550-8
024 7 _a10.1007/0-387-48550-3
_2doi
050 4 _aTK7888.4
072 7 _aTJFC
_2bicssc
072 7 _aTEC008010
_2bisacsh
082 0 4 _a621.3815
_223
100 1 _aSaxena, Prashant.
245 1 0 _aRouting Congestion in VLSI Circuits: Estimation and Optimization
_h[electronic resource] /
_cby Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar.
260 _aBoston, MA :
_bSpringer US,
_c2007.
300 _bdigital.
490 0 _aSeries on Integrated Circuits and Systems,
_x1558-9412
650 0 _aEngineering.
650 0 _aComputer aided design.
650 0 _aTelecommunication.
650 0 _aSystems engineering.
650 1 4 _aEngineering.
650 2 4 _aCircuits and Systems.
650 2 4 _aComputer-Aided Engineering (CAD, CAE) and Design.
650 2 4 _aCommunications Engineering, Networks.
700 1 _aShelar, Rupesh S.
700 1 _aSapatnekar, Sachin S.
710 2 _aSpringerLink (Online service)
773 0 _tSpringer eBooks
776 0 8 _iPrinted edition:
_z9780387300375
830 0 _aSeries on Integrated Circuits and Systems,
_x1558-9412
856 4 0 _uhttp://dx.doi.org/10.1007/0-387-48550-3
912 _aZDB-2-ENG
999 _c67183
_d67183