000 | 03457nam a22004695i 4500 | ||
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001 | 978-90-481-3631-5 | ||
003 | DE-He213 | ||
005 | 20140220084559.0 | ||
007 | cr nn 008mamaa | ||
008 | 100301s2010 ne | s |||| 0|eng d | ||
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_a9789048136315 _9978-90-481-3631-5 |
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024 | 7 |
_a10.1007/978-90-481-3631-5 _2doi |
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050 | 4 | _aTK7888.4 | |
072 | 7 |
_aTJFC _2bicssc |
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072 | 7 |
_aTEC008010 _2bisacsh |
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082 | 0 | 4 |
_a621.3815 _223 |
100 | 1 |
_aGroße, Daniel. _eauthor. |
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245 | 1 | 0 |
_aQuality-Driven SystemC Design _h[electronic resource] / _cby Daniel Große, Rolf Drechsler. |
264 | 1 |
_aDordrecht : _bSpringer Netherlands, _c2010. |
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300 |
_aXIX, 170p. _bonline resource. |
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336 |
_atext _btxt _2rdacontent |
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337 |
_acomputer _bc _2rdamedia |
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338 |
_aonline resource _bcr _2rdacarrier |
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_atext file _bPDF _2rda |
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505 | 0 | _aPreliminaries -- System-Level Verification -- Block-Level Verification -- Top-Level Verification -- Summary and Conclusions. | |
520 | _aFaced with the steadily increasing complexity and rapidly shortening time-to-market requirements designing electronic systems is a very challenging task. To manage this situation effectively the level of abstraction in modeling has been raised during the past years in the computer aided design community. Meanwhile, for the so-called system-level design the system description language SystemC has become the de facto standard. However, while modeling from abstract to synthesizable descriptions in combination with specification concepts like Transaction Level Modeling (TLM) leads to very good results, the verification quality is poor. The two main reasons are that (1) the existing SystemC verification techniques do not escort the different abstraction levels effectively and (2) in particular the resulting quality in terms of the covered functionality is only checked manually. Hence, due to the increasing design complexity the number of undetected errors is growing rapidly. Therefore a quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results. | ||
650 | 0 | _aEngineering. | |
650 | 0 | _aComputer science. | |
650 | 0 | _aSoftware engineering. | |
650 | 0 | _aSystems engineering. | |
650 | 1 | 4 | _aEngineering. |
650 | 2 | 4 | _aCircuits and Systems. |
650 | 2 | 4 | _aSoftware Engineering/Programming and Operating Systems. |
650 | 2 | 4 | _aRegister-Transfer-Level Implementation. |
700 | 1 |
_aDrechsler, Rolf. _eauthor. |
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710 | 2 | _aSpringerLink (Online service) | |
773 | 0 | _tSpringer eBooks | |
776 | 0 | 8 |
_iPrinted edition: _z9789048136308 |
856 | 4 | 0 | _uhttp://dx.doi.org/10.1007/978-90-481-3631-5 |
912 | _aZDB-2-ENG | ||
999 |
_c113399 _d113399 |