000			03031nam a22004455i 4500
001			978-1-4419-6481-6
003			DE-He213
005			20140220084509.0
007			cr nn 008mamaa
008			100726s2010 xxu| s |||| 0|eng d
020			_a9781441964816 _9978-1-4419-6481-6
024	7		_a10.1007/978-1-4419-6481-6 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aSingh, Gaurav. _eauthor.
245	1	0	_aLow Power Hardware Synthesis from Concurrent Action-Oriented Specifications _h[electronic resource] / _cby Gaurav Singh, Sandeep K. Shukla.
264		1	_aNew York, NY : _bSpringer New York, _c2010.
300			_aX, 240p. 200 illus., 100 illus. in color. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aRelated Work -- Background -- Low-Power Problem Formalization -- Heuristics for Power Savings -- Complexity Analysis of Scheduling in CAOS-Based Synthesis -- Dynamic Power Optimizations -- Peak Power Optimizations -- Verifying Peak Power Optimizations Using SPIN Model Checker -- Epilogue.
520			_aLow Power Hardware Synthesis from Concurrent Action-Oriented Specifications Gaurav Singh Sandeep K. Shukla This book introduces novel techniques for generating low-power hardware from a high-level description of a design in terms of Concurrent Action-Oriented Specifications (CAOS). It also describes novel techniques for formal verification of such designs. It will provide the readers with definitions of various power optimization and formal verification problems related to CAOS-based synthesis, necessary background concepts, techniques to generate hardware according to the design’s power requirements, and detailed experimental results obtained by applying the techniques introduced on realistic hardware designs. •Presents detailed analysis of various power optimization problems associated with high-level synthesis, as well as novel techniques for reducing power consumption of hardware designs at a higher level of abstraction; •Discusses various formal verification issues associated with synthesizing different possible versions of a hardware design (differing in their latency, area, and/or power consumption); •Includes detailed experimental results obtained by applying the techniques introduced on benchmark hardware designs.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aShukla, Sandeep K. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441964809
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-6481-6
912			_aZDB-2-ENG
999			_c110645 _d110645