000			04915nam a22004815i 4500
001			978-1-4419-0950-3
003			DE-He213
005			20140220084503.0
007			cr nn 008mamaa
008			100301s2010 xxu| s |||| 0|eng d
020			_a9781441909503 _9978-1-4419-0950-3
024	7		_a10.1007/978-1-4419-0950-3 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aJayakumar, Nikhil. _eauthor.
245	1	0	_aMinimizing and Exploiting Leakage in VLSI Design _h[electronic resource] / _cby Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri.
264		1	_aBoston, MA : _bSpringer US, _c2010.
300			_bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aLeakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes -- Existing Leakage Minimization Approaches -- Computing Leakage Current Distributions -- Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities -- The HL Approach: A Low-Leakage ASIC Design Methodology -- Simultaneous Input Vector Control and Circuit Modification -- Optimum Reverse Body Biasing for Leakage Minimization -- I: Conclusions and Future Directions -- Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design -- Exploiting Leakage: Sub-threshold Circuit Design -- Adaptive Body Biasing to Compensate for PVT Variations -- Optimum VDD for Minimum Energy -- Reclaiming the Sub-threshold Speed Penalty Through Micropipelining -- II: Conclusions and Future Directions -- Design of a Sub-threshold BFSK Transmitter IC -- Design of the Chip -- Implementation of the Chip -- Experimental Results.
520			_aMinimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book. Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage. Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design. Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aPaul, Suganth. _eauthor.
700	1		_aGarg, Rajesh. _eauthor.
700	1		_aGulati, Kanupriya. _eauthor.
700	1		_aKhatri, Sunil P. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441909497
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-0950-3
912			_aZDB-2-ENG
999			_c110283 _d110283