000			03646nam a22004695i 4500
001			978-1-4419-7958-2
003			DE-He213
005			20140220083726.0
007			cr nn 008mamaa
008			110110s2011 xxu| s |||| 0|eng d
020			_a9781441979582 _9978-1-4419-7958-2
024	7		_a10.1007/978-1-4419-7958-2 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aHoriguchi, Masashi. _eauthor.
245	1	0	_aNanoscale Memory Repair _h[electronic resource] / _cby Masashi Horiguchi, Kiyoo Itoh.
264		1	_aNew York, NY : _bSpringer New York : _bImprint: Springer, _c2011.
300			_aX, 218 p. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
490	1		_aIntegrated Circuits and Systems, _x1558-9412
505	0		_aAn Introduction to Repair Techniques: Basics of Redundancy -- Basics of Error Checking and Correction -- Comparison between Redundancy and ECC -- Repairs of Logic Circuits -- Redundancy: Models of Fault Distribution -- Yield Improvement through Redundancy -- Replacement Schemes -- Intra-Subarray Replacement -- Inter-Subarray Replacement -- Subarray Replacement -- Devices for Storing Addresses -- Testing for Redundancy -- Error Checking and Correction: Linear Algebra and Linear Codes -- Galois Field -- Error-Correcting Codes -- Coding and Decoding Circuits -- Theoretical Reduction in Soft-Error and Hard-Error Rates -- Application of ECC -- Testing for ECC -- Synergistic Effect of Redundancy and ECC: Repair of Bit Faults using Synergistic Effect -- Application of Synergistic Effect.
520			_aYield and reliability of memories have degraded with device and voltage scaling in the nano-scale era, due to ever-increasing hard/soft errors and device parameter variations. As a result, repair techniques have been indispensable for nano-scale memories. Without these techniques, even modern MPUs/ SoCs, in which memories have dominated the area and performance, could not have been designed successfully. This book systematically describes these yield and reliability issues in terms of mathematics and engineering, as well as an array of repair techniques, based on the authors’ long careers in developing memories and low-voltage CMOS circuits. Nanoscale Memory Repair gives a detailed explanation of the various yield models and calculations, as well as various, practical logic and circuits that are critical for higher yield and reliability.  Presents the first comprehensive reference to reliability and repair techniques for nano-scale memories; Covers both the mathematical foundations and engineering applications of yield and reliability in nano-scale memories; Includes a variety of practical circuits and logic, critical for higher yield and reliability, which have been proven successful during the authors’ extensive experience in developing memories and low-voltage CMOS circuits.
650		0	_aEngineering.
650		0	_aComputer aided design.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
700	1		_aItoh, Kiyoo. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781441979575
830		0	_aIntegrated Circuits and Systems, _x1558-9412
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4419-7958-2
912			_aZDB-2-ENG
999			_c105899 _d105899