000			03485nam a22005055i 4500
001			978-1-4614-0715-7
003			DE-He213
005			20140220083239.0
007			cr nn 008mamaa
008			120213s2012 xxu| s |||| 0|eng d
020			_a9781461407157 _9978-1-4614-0715-7
024	7		_a10.1007/978-1-4614-0715-7 _2doi
050		4	_aTK7888.4
072		7	_aTJFC _2bicssc
072		7	_aTEC008010 _2bisacsh
082	0	4	_a621.3815 _223
100	1		_aSpear, Chris. _eauthor.
245	1	0	_aSystemVerilog for Verification _h[electronic resource] : _bA Guide to Learning the Testbench Language Features / _cby Chris Spear, Greg Tumbush.
250			_a3rd ed. 2012.
264		1	_aBoston, MA : _bSpringer US : _bImprint: Springer, _c2012.
300			_aXLIII, 464 p. 720 illus. _bonline resource.
336			_atext _btxt _2rdacontent
337			_acomputer _bc _2rdamedia
338			_aonline resource _bcr _2rdacarrier
347			_atext file _bPDF _2rda
505	0		_aVerification Guidelines -- Data Types -- Procedural Statements and Routines -- Connecting the Testbench and Design -- Basic OOP -- Randomization -- Threads and Interprocess Communication -- Advanced OOP and Testbench Guidelines -- Functional Coverage -- Advanced Interfaces -- A Complete SystemVerilog Testbench -- Interfacing with C/C++.
520			_aBased on the highly successful second edition, this extended edition of SystemVerilog for Verification: A Guide to Learning the Testbench Language Features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. It contains materials for both the full-time verification engineer and the student learning this valuable skill. In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and then use that context to demonstrate the language features,  including the advantages and disadvantages of different styles, allowing readers to choose between alternatives. This textbook contains end-of-chapter exercises designed to enhance students’ understanding of the material. Other features of this revision include: New sections on static variables, print specifiers, and DPI from the 2009 IEEE language standard Descriptions of UVM features such as factories, the test registry, and the configuration database Expanded code samples and explanations Numerous samples that have been tested on the major SystemVerilog simulators SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Third Edition is suitable for use in a one-semester SystemVerilog course on SystemVerilog at the undergraduate or graduate level. Many of the improvements to this new edition were compiled through feedback provided from hundreds of readers.
650		0	_aEngineering.
650		0	_aComputer hardware.
650		0	_aComputer aided design.
650		0	_aComputer engineering.
650		0	_aSystems engineering.
650	1	4	_aEngineering.
650	2	4	_aCircuits and Systems.
650	2	4	_aComputer-Aided Engineering (CAD, CAE) and Design.
650	2	4	_aComputer Hardware.
650	2	4	_aElectrical Engineering.
700	1		_aTumbush, Greg. _eauthor.
710	2		_aSpringerLink (Online service)
773	0		_tSpringer eBooks
776	0	8	_iPrinted edition: _z9781461407140
856	4	0	_uhttp://dx.doi.org/10.1007/978-1-4614-0715-7
912			_aZDB-2-ENG
999			_c100909 _d100909