Multi-Objective Optimization in Physical Synthesis of Integrated Circuits (Record no. 94902)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 03468nam a22004815i 4500 |
| 001 - CONTROL NUMBER | |
| control field | 978-1-4614-1356-1 |
| 003 - CONTROL NUMBER IDENTIFIER | |
| control field | DE-He213 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20140220082811.0 |
| 007 - PHYSICAL DESCRIPTION FIXED FIELD--GENERAL INFORMATION | |
| fixed length control field | cr nn 008mamaa |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 120807s2013 xxu| s |||| 0|eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9781461413561 |
| -- | 978-1-4614-1356-1 |
| 024 7# - OTHER STANDARD IDENTIFIER | |
| Standard number or code | 10.1007/978-1-4614-1356-1 |
| Source of number or code | doi |
| 050 #4 - LIBRARY OF CONGRESS CALL NUMBER | |
| Classification number | TK7888.4 |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TJFC |
| Source | bicssc |
| 072 #7 - SUBJECT CATEGORY CODE | |
| Subject category code | TEC008010 |
| Source | bisacsh |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.3815 |
| Edition number | 23 |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | A. Papa, David. |
| Relator term | author. |
| 245 10 - TITLE STATEMENT | |
| Title | Multi-Objective Optimization in Physical Synthesis of Integrated Circuits |
| Medium | [electronic resource] / |
| Statement of responsibility, etc | by David A. Papa, Igor L. Markov. |
| 264 #1 - | |
| -- | New York, NY : |
| -- | Springer New York : |
| -- | Imprint: Springer, |
| -- | 2013. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | IX, 155 p. 61 illus. |
| Other physical details | online resource. |
| 336 ## - | |
| -- | text |
| -- | txt |
| -- | rdacontent |
| 337 ## - | |
| -- | computer |
| -- | c |
| -- | rdamedia |
| 338 ## - | |
| -- | online resource |
| -- | cr |
| -- | rdacarrier |
| 347 ## - | |
| -- | text file |
| -- | |
| -- | rda |
| 490 1# - SERIES STATEMENT | |
| Series statement | Lecture Notes in Electrical Engineering, |
| International Standard Serial Number | 1876-1100 ; |
| Volume number/sequential designation | 166 |
| 505 0# - FORMATTED CONTENTS NOTE | |
| Formatted contents note | Part I: Introduction and Prior Art -- Timing Closure for Multi-Million-Gate Integrated Circuits -- State of the Art in Physical Synthesis -- Part II: Local Physical Synthesis and Necessary Analysis Techniques -- Buffer Insertion during Timing-Driven Placement -- Bounded Transactional Timing Analysis -- Gate Sizing During Timing-Driven Placement -- Part III: Broadening the Scope of Circuit Transformations -- Physically-Driven Logic Restructuring -- Logic Restructuring as an Aid to Physical Retiming -- Broadening the Scope of Optimization using Partitioning -- Co-Optimization of Latches and Clock Networks -- Conclusions and Future Work. |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc | This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products. It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima; Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization techniques that ensure a graceful timing closure process and impact nearly every aspect of a typical physical synthesis flow. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronics. |
| 650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Systems engineering. |
| 650 14 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Engineering. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Circuits and Systems. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Electronics and Microelectronics, Instrumentation. |
| 650 24 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name as entry element | Nanotechnology and Microengineering. |
| 700 1# - ADDED ENTRY--PERSONAL NAME | |
| Personal name | L. Markov, Igor. |
| Relator term | author. |
| 710 2# - ADDED ENTRY--CORPORATE NAME | |
| Corporate name or jurisdiction name as entry element | SpringerLink (Online service) |
| 773 0# - HOST ITEM ENTRY | |
| Title | Springer eBooks |
| 776 08 - ADDITIONAL PHYSICAL FORM ENTRY | |
| Display text | Printed edition: |
| International Standard Book Number | 9781461413554 |
| 830 #0 - SERIES ADDED ENTRY--UNIFORM TITLE | |
| Uniform title | Lecture Notes in Electrical Engineering, |
| -- | 1876-1100 ; |
| Volume number/sequential designation | 166 |
| 856 40 - ELECTRONIC LOCATION AND ACCESS | |
| Uniform Resource Identifier | http://dx.doi.org/10.1007/978-1-4614-1356-1 |
| 912 ## - | |
| -- | ZDB-2-ENG |
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