Ruiz-Amaya, Jesús.
Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs [electronic resource] / by Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez. - XIII, 209p. 146 illus. online resource.
Pipeline ADC Overview -- Design Methodologies for Pipeline ADCs -- Pipeline ADC Electrical-level Synthesis Tool -- Behavioural Modeling of Pipeline ADCs -- Case Study: Design of a 10BIT@60MS Pipeline ADC -- Experimental Results and State of the Art -- Conclusions and Future Lines of Research.
This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters. Describes efficient procedures for heirarchical top-down design of pipeline converters; Presents new methodologies to reduce bottom-up iterations, through inherent embedding of transistor-level parameters, such as parasitic capacitances, transconductances, and saturation currents; Provides mathematical details of behavioral models, includes descriptions of the synthesis methods and associated tools and illustrates models through case studies supported by silicon prototypes.
9781441988461
10.1007/978-1-4419-8846-1 doi
Engineering.
Computer science.
Systems engineering.
Engineering.
Circuits and Systems.
Signal, Image and Speech Processing.
Processor Architectures.
TK7888.4
621.3815
Device-Level Modeling and Synthesis of High-Performance Pipeline ADCs [electronic resource] / by Jesús Ruiz-Amaya, Manuel Delgado-Restituto, Ángel Rodríguez-Vázquez. - XIII, 209p. 146 illus. online resource.
Pipeline ADC Overview -- Design Methodologies for Pipeline ADCs -- Pipeline ADC Electrical-level Synthesis Tool -- Behavioural Modeling of Pipeline ADCs -- Case Study: Design of a 10BIT@60MS Pipeline ADC -- Experimental Results and State of the Art -- Conclusions and Future Lines of Research.
This book presents models and procedures to design pipeline analog-to-digital converters, compensating for device inaccuracies, so that high-performance specs can be met within short design cycles. These models are capable of capturing and predicting the behavior of pipeline data converters within less than half-a-bit deviation, versus transistor-level simulations. As a result, far fewer model iterations are required across the design cycle. Models described in this book accurately predict transient behaviors, which are key to the performance of discrete-time systems and hence to the performance of pipeline data converters. Describes efficient procedures for heirarchical top-down design of pipeline converters; Presents new methodologies to reduce bottom-up iterations, through inherent embedding of transistor-level parameters, such as parasitic capacitances, transconductances, and saturation currents; Provides mathematical details of behavioral models, includes descriptions of the synthesis methods and associated tools and illustrates models through case studies supported by silicon prototypes.
9781441988461
10.1007/978-1-4419-8846-1 doi
Engineering.
Computer science.
Systems engineering.
Engineering.
Circuits and Systems.
Signal, Image and Speech Processing.
Processor Architectures.
TK7888.4
621.3815